
                                 BackAnnotation
                                 --------------

                        02:16 PM Wednesday, May 19, 2021
Job Name: C:\projects\_UT_Scintilla\EEVX2PADSPRO\PPVX2.8.1\Tx_Rx_433MHz_V2.0\PCB\Board1.pcb


  Updating Logic Database...

     Version:  99.00.05

     No changes made to Existing Schematic Packaging.


     There is no symbol data to be back annotated to the schematic source.


     The Logic DataBase has been updated and the Common DataBase has
      automatically been brought into sync with the Logic DataBase.
      Please proceed with your design.

     Finished updating the Logic Database.

     Updating the CDB Properties
     Finished updating the CDB Properties

     Updating LogicDB Version from 1 to 2.

     Creating a formatted Schematic Netlist (LogFiles\AfterBakAnnoNetlist.txt)...
     A formatted Schematic Netlist has been created.

            Creating a new netlist text file (LogFiles\KeyinNetList.txt)
            from the Logic Database (Work\Layout_Temp\LogicDB.lgc)...
  A new netlist text file has been generated.

     Completed Back Annotation
