
                     PCB Job Preferences to Design Data Log
                     --------------------------------------

                          11:39 AM Friday, May 15, 2020
                                   Job Name: 


Linear values will be specified in the following units: IN

Creating Job Preferences Design Data file 'C:\projects\UT_Sintilla\Board_Design_VX2.7.2\Tx_Rx_433MHz_15may2020\PCB\Output\ODBpp\ut__scintilla_workshop_v1.0_odb_15may2020\user\layerstackup.usr'.

Job Preferences Design Data file 'C:\projects\UT_Sintilla\Board_Design_VX2.7.2\Tx_Rx_433MHz_15may2020\PCB\Output\ODBpp\ut__scintilla_workshop_v1.0_odb_15may2020\user\layerstackup.usr' was successfully created.

                     PCB Job Preferences to Design Data Log
                     --------------------------------------

                          11:41 AM Friday, May 15, 2020
                                   Job Name: 


Linear values will be specified in the following units: IN

Creating Job Preferences Design Data file 'C:\projects\UT_Sintilla\Board_Design_VX2.7.2\Tx_Rx_433MHz_15may2020\PCB\Output\ODBpp\ut__scintilla_workshop_v1.0_odb_15may2020\user\layerstackup.usr'.

Job Preferences Design Data file 'C:\projects\UT_Sintilla\Board_Design_VX2.7.2\Tx_Rx_433MHz_15may2020\PCB\Output\ODBpp\ut__scintilla_workshop_v1.0_odb_15may2020\user\layerstackup.usr' was successfully created.

                     PCB Job Preferences to Design Data Log
                     --------------------------------------

                          01:11 PM Friday, May 15, 2020
                                   Job Name: 


Linear values will be specified in the following units: IN

Creating Job Preferences Design Data file 'C:\projects\UT_Sintilla\Board_Design_VX2.7.2\Tx_Rx_433MHz_15may2020\PCB\Output\ODBpp\ut_scintilla_workshop_v1.0_odb_15may2020\user\layerstackup.usr'.

Job Preferences Design Data file 'C:\projects\UT_Sintilla\Board_Design_VX2.7.2\Tx_Rx_433MHz_15may2020\PCB\Output\ODBpp\ut_scintilla_workshop_v1.0_odb_15may2020\user\layerstackup.usr' was successfully created.

                     PCB Job Preferences to Design Data Log
                     --------------------------------------

                          01:14 PM Friday, May 15, 2020
                                   Job Name: 


Linear values will be specified in the following units: IN

Creating Job Preferences Design Data file 'C:\projects\UT_Sintilla\Board_Design_VX2.7.2\Tx_Rx_433MHz_15may2020\PCB\Output\ODBpp\ut_scintilla_workshop_v1.0_odb_15may2020\user\layerstackup.usr'.

Job Preferences Design Data file 'C:\projects\UT_Sintilla\Board_Design_VX2.7.2\Tx_Rx_433MHz_15may2020\PCB\Output\ODBpp\ut_scintilla_workshop_v1.0_odb_15may2020\user\layerstackup.usr' was successfully created.

                     PCB Job Preferences to Design Data Log
                     --------------------------------------

                          01:18 PM Friday, May 15, 2020
                                   Job Name: 


Linear values will be specified in the following units: IN

Creating Job Preferences Design Data file 'C:\projects\UT_Sintilla\Board_Design_VX2.7.2\Tx_Rx_433MHz_15may2020\PCB\Output\ODBpp\ut_scintilla_workshop_v1.0_odb_15may2020\user\layerstackup.usr'.

Job Preferences Design Data file 'C:\projects\UT_Sintilla\Board_Design_VX2.7.2\Tx_Rx_433MHz_15may2020\PCB\Output\ODBpp\ut_scintilla_workshop_v1.0_odb_15may2020\user\layerstackup.usr' was successfully created.

                     PCB Job Preferences to Design Data Log
                     --------------------------------------

                          01:43 PM Friday, May 15, 2020
                                   Job Name: 


Linear values will be specified in the following units: IN

Creating Job Preferences Design Data file 'C:\projects\UT_Sintilla\Board_Design_VX2.7.2\Tx_Rx_433MHz_15may2020\PCB\Output\ODBpp\ut_scintilla_workshop_v1.0_odb_15may2020\user\layerstackup.usr'.

Job Preferences Design Data file 'C:\projects\UT_Sintilla\Board_Design_VX2.7.2\Tx_Rx_433MHz_15may2020\PCB\Output\ODBpp\ut_scintilla_workshop_v1.0_odb_15may2020\user\layerstackup.usr' was successfully created.

                     PCB Job Preferences to Design Data Log
                     --------------------------------------

                          03:14 PM Monday, May 17, 2021
                                   Job Name: 


Linear values will be specified in the following units: IN

Creating Job Preferences Design Data file 'Z:\project_non_backup\UT_Scintilla\LayoutWorkshop\Board_Design_VX2.7.2\Tx_Rx_433MHz_V1.1_work\PCB\Output\ODBpp\ut_scintilla_workshop_v2.0_odb_17may2021\user\layerstackup.usr'.

Job Preferences Design Data file 'Z:\project_non_backup\UT_Scintilla\LayoutWorkshop\Board_Design_VX2.7.2\Tx_Rx_433MHz_V1.1_work\PCB\Output\ODBpp\ut_scintilla_workshop_v2.0_odb_17may2021\user\layerstackup.usr' was successfully created.

                     PCB Job Preferences to Design Data Log
                     --------------------------------------

                          03:20 PM Monday, May 17, 2021
                                   Job Name: 


Linear values will be specified in the following units: IN

Creating Job Preferences Design Data file 'Z:\project_non_backup\UT_Scintilla\LayoutWorkshop\Board_Design_VX2.7.2\Tx_Rx_433MHz_V1.1_work\PCB\Output\ODBpp\ut_scintilla_workshop_v2.0_odb_17may2021\user\layerstackup.usr'.

Job Preferences Design Data file 'Z:\project_non_backup\UT_Scintilla\LayoutWorkshop\Board_Design_VX2.7.2\Tx_Rx_433MHz_V1.1_work\PCB\Output\ODBpp\ut_scintilla_workshop_v2.0_odb_17may2021\user\layerstackup.usr' was successfully created.

                     PCB Job Preferences to Design Data Log
                     --------------------------------------

                          03:26 PM Monday, May 17, 2021
                                   Job Name: 


Linear values will be specified in the following units: IN

Creating Job Preferences Design Data file 'Z:\project_non_backup\UT_Scintilla\LayoutWorkshop\Board_Design_VX2.7.2\Tx_Rx_433MHz_V1.1_work\PCB\Output\ODBpp\ut_scintilla_workshop_v2.0_odb_17may2021\user\layerstackup.usr'.

Job Preferences Design Data file 'Z:\project_non_backup\UT_Scintilla\LayoutWorkshop\Board_Design_VX2.7.2\Tx_Rx_433MHz_V1.1_work\PCB\Output\ODBpp\ut_scintilla_workshop_v2.0_odb_17may2021\user\layerstackup.usr' was successfully created.
